1. Field of the Invention
The present invention relates to systems and methods for protecting integrated circuits from reverse engineering and in particular to a building block for a logic cell library that is strongly resistant to reverse engineering.
2. Description of the Related Art
In a conventional CMOS cell library, every logic cell has a unique way of interconnecting its devices (its schematic) which is well known to technical personnel familiar with CMOS circuit design. For example, a NAND gate has the P-channel devices connected in parallel and the N-channel devices connected in series, and a NOR gate has P-channel devices connected in series and N-channel devices connected in parallel.
An exemplary schematic of a standard 2-input NAND gate and a 2-input NOR gate, includes P devices 10 and N devices 11, are shown in FIG. 1. Reverse engineers can use this valuable information to identify the function of each logic gate and thus are able to extract the complete ASIC design. What is needed is a method and apparatus for making reverse engineering of circuits more difficult. The present invention satisfies that need by presenting a circuit block that can be used for a wide variety of logical functions. One attempting to reverse engineer an ASIC designed with logic gates as described herein faces a large number of identical circuit blocks and will not be able to find any obvious clue for logic function identification.